As illustrated on FIGS. 1 and 2, delta-sigma analog-to-digital converters 1 for generating a digital signal 100 as a function of a first analog signal 101 and a clock signal having a first phase and a second phase are well-known which comprise:                a first branch 11 on which is arranged an input resistance 111 for applying a second analog input signal 1011,        a feedback branch 12 for feeding back a third analog reference signal 1012, said feedback branch including a digital-to-analog converter 121 arranged for generating said third analog reference signal as a function of the digital signal,        a loop filter 13 for generating an integrated signal 103 as a function of said first analog signal, said loop filter being coupled to a branch point 14 of said first and feedback branches for receiving said first analog signal, and        a quantizer 15 for generating said digital signal as a function of said integrated signal, the quantizer being coupled to the loop filter for receiving the integrated signal and coupled to said feedback branch for delivering said digital signal to said digital-to-analog converter.        
Such delta-sigma analog-to-digital converters allow to achieve a high-speed and high-resolution analog-to-digital conversion, without requiring front-end sampling/hold elements (but only an input resistance 111) and with presenting an intrinsic anti-aliasing filter. Moreover, the use of said digital-to-analog converter implemented with a switched-capacitor circuit 1211 allows to reduce significantly the sensitivity to clock jitter. Thus, such switched-capacitor circuit is often privileged. Unfortunately, such digital-to-analog converter increases the power consumption of the delta-sigma analog-to-digital converters 1, to be able to conserve the conversion resolution. The reason of this drawback is explained hereafter.
In order to guarantee a satisfying input voltage/current conversion, the input potential of the loop filter 13 must remain constant whatever the first analog signal transmits. Logically, the input potential of the loop filter is equal to its exit potential divided by its gain taken to the first analog signal frequency, with the gain being low at high frequencies; now the quick discharge of the digital-to-analog converter attracts said loop filter towards high frequencies, therefore the input potential oscillates. It is said that the input voltage/current is impacted by noisy virtual ground. And that is how the performances of the delta-sigma analog-to-digital converter are degraded. To clean the noisy virtual ground in order to maintain the conversion resolution, the power consumption of the loop filter, then the power consumption of the delta-sigma analog-to-digital converter, should be increased.
A solution has been proposed which allows to just reduce the attraction of the loop filter towards high frequencies. More particularly, as mentioned in the Prior Art part of U.S. Pat. No. 7,151,474 and as illustrated on FIG. 3, it has been proposed to discharge the digital-to-analog converter via an additional resistance 17. Effectively, this solution allows to reduce the high frequency components of the third analog reference signal. Nonetheless, this solution is not satisfying because on the one hand the sensitivity of the delta-sigma analog-to-digital converter to clock jitter is consequently increased, on the other hand the less quick discharge of the switched-capacitor circuit can lead to the transmission of a charge error to the loop filter. These phenomena can be explained with more details as follow.
Logically, the discharge time of the digital-to-analog converter 121 depends on said additional resistance 17: the more the additional resistance increases (in order to greatly reduce said high frequency components of the third analog reference signal), the more the discharge time of the digital-to-analog converter increases. As illustrated on FIG. 4, when said discharge time becomes larger than the clock signal 102, the discharge of the digital-to-analog converter becomes incomplete before subsequent integration. Then a charge error 31 is transmitted to the loop filter, which in turn increases the sensitivity of the delta-sigma analog-to-digital converter to clock jitter 30.
Thus, such delta-sigma analog-to-digital converters do not allow to keep the clock jitter immunity, provided by the use of such digital-to-analog converter, without requiring an increase of their power consumption. Then, there is a need for a delta-sigma analog-to-digital converter which provides a satisfying trade-off between power consumption saving and clock jitter immunity.